Site icon The Passive Times

3D IC hybrid bonding workflow to validate stacked designs

Siemens Digital Industries Software has collaborated with semiconductor foundry United Microelectronics (UMC) to develop and implement a multi-chip 3D IC planning, assembly validation and parasitic extraction (PEX) workflow for the foundry’s wafer-on-wafer and chip-on-wafer technologies.  Stacking silicon die or chiplets on top of each other in a single packaged device allows companies to achieve the […]

The post 3D IC hybrid bonding workflow to validate stacked designs appeared first on Softei.com – Global Electronics Industry News.

Read More
Softei.com – Global Electronics Industry News

Exit mobile version