Linting tool supports automatic conversion for Microchip and SoC FPGAs 

Mixed HDL language simulation and hardware-assisted verification company, Aldec, has updated its Alint-Pro linting tool to enhance the support of Microchip Technology’s Libero SoC design suite. The new release supports automatic conversion of Libero projects into Alint-Pro’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog. […]

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