Native J-Link debug probe support for selected Cadence Tensilica Processor IP DSPs is now available for SeggerJ-Link models. The Cadence Tensilica cores supported in the first implementation phase are the Tensilica Xtensa LX7 CPU, a number of Tensilica HiFi DSPs (HiFi 4, HiFi 3z, HiFi 3, and HiFi 1) and the Tensilica Fusion F1 DSP. […]
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